��оделирование накопления заряда в облученных моп/кни транзисторах

The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.