Simulação de Redes Reguladoras de Genes com Lógica Booleana e Limiar em Plataformas Alto Desempenho

Gene regulatory networks are graph-based models widely used to study cell behavior, cell differentiation processes, or the treatment and evolution of the disease. A network is a graph where each node is a gene, and the gene behavior is described by boolean equations. The network simulations evaluate these equations several times throughout the execution. The network states’ transitions are the basic step in gene regulatory algorithms. This paper proposes a study of the CPU, GPU and FPGA implementations of the basic operation which is the calculation of the next state. We explore OpenMP and AVX vectorization compiler-based approaches for processors. Moreover, we propose a new dynamic overlay architecture to simplify the use of FPGA solutions. In addition, we transform the Boolean equation in threshold logic. Finally, we evaluate 16 gene regulatory networks used in the literature. The experimental results show a speed-up from 3× to 90× with respect to the CPU times. The AVX/OpenMP, GPU and FPGA implementations report a speed-up of 3x, 57.3x, and 86.7x, respectively.