A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail G m -Boosting Technique

One of the most key analog blocks in VLSI is probably the buffer amplifier dedicated to driving large off-chip loads. However, achieving fast settling-time and high output current drivability over a wide input voltage range has been challenging with low quiescent current $(I_{Q})$ consumption. In energy-efficient amplifier designs, many technical breakthroughs have been made to enhance slew-rate (SR) [1] –[5] and wide unity-gain bandwidth (GBW) [4] –[6], thus far. However, prior efforts of [1], [2], [4] –[6] might be impractical to use in high-voltage $(\ge 5\mathrm{V})$ actuators and flat-panel displays due to their limited (no rail-to-rail) input range with low supply voltage. Despite obtaining good SR and GBW, the works of [1] –[3] allowed a considerable overshoot in transient response, which can impose sudden voltage stress on the load. Besides, complex stability compensation in a three-stage amplifier [6] inherently restrains achieving high SR. To overcome such technical limits with optimal transient response, this paper presents a low $- \mathrm{I}_{Q}$ ultra-high-SR amplifier with rail-to-rail transconductance $(G_{m}) -$ boosting technique.