Sample Mounting Methods for Precision Delayering of 130 nm Integrated Circuit Devices
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)（2020）
Abstract
This paper reviews different methods for mounting and integrated circuit (IC) for delayering. In this work, several 130nm technology devices are observed during the delayering process as a means of evaluating the advantages and disadvantages of various mounting techniques. Suitability for chemical mechanical polishing, wet etching, and dry etching is considered.
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Key words
integrated circuit delayering,chemical mechanical polishing,sample preparation
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