Computation-efficient and compact FPGA design for a real-time wearable arrhythmia-detector

Abstract The epidemic of diabetes, obesity and unhealthy lifestyles have highly contributed to increasing number of patients with heart problems. Wearable fitness trackers are not accurate enough in heart problem detection and the current software-based algorithms, when implemented in devices like smartwatches are not efficient in terms of hardware resource utilization and computational speed. To address these limitations, this paper proposes an automated heartbeat classifying hardware chip-design which can be placed in any kind of wearable device for real-time cardiac monitoring that would help to ensure early diagnosis of any kind of cardiac abnormality. The algorithm burnt on the hardware is a modification of the Pan-Tompkins beat-detection algorithm to which a novel classifier algorithm is added. It exhibits high computational speed with an accuracy of 99.65% in extremely noisy situations, when applied on the MIT/BIH arrhythmia database. The hardware utilization on the SPARTAN-6 FPGA for the presented design is just 32% allowing space for much more multi-tasking and upgrading to be done when implemented on a wearable device as an ASIC.