FPGA-orthopoly: a hardware implementation of orthogonal polynomials

There are many algorithms based on orthogonal functions that can be applied to real-world problems. For example, many of them can be reduced to approximate the solution of a dynamical system, and the approximation can be done with orthogonal functions. But calculating the orthogonal functions is very time-consuming, there are many difficulties in implementation of them and because of these drawbacks, they are not utilized in real applications. For the purpose of solving this issue and filling the gap between the theory and real applications, in this paper, an FPGA implementation of some classical orthogonal polynomials families is presented. Here, hardware architectures of the first and second kinds of Chebyshev, Jacobi, Legendre, Gegenbauer, Laguerre, and Hermit polynomials are presented. The experiments show that the presented architectures are low power, fast, and with a small circuit area. The obtained results show a 10.5 × speed-up in the best case, 1.5 × speed-up in the worst case, and at least 47