A Low Sampling Rate Memory-Grouped Method for Digital Predistortion With Constrained Acquisition Bandwidth

A novel memory-grouped method is proposed for digital predistortion (DPD) of power amplifiers (PAs) with constrained acquisition bandwidth (BW) and extremely low sampling rate. By grouping the basis functions with different memory delays, a two-step algorithm can reduce overfitting in the constrained-BW technique. As a result, excellent DPD performance can be achieved even when the acquisition BW is constrained to several times narrower than the BW of the original input signal. Thus, using the memory-grouped method, a very low-speed analog-to-digital converter (ADC) can be used to sample the constrained feedback signal without aliasing, significantly reducing the cost of configuring a high-speed ADC. The performance of the proposed method is compared with the existing methods in different scenarios. Experimental results show that when the feedback BW is less than the BW of the original input signal, the proposed method can still achieve good performance, while the traditional methods fail to work. The experiment results also imply that the memory-grouped method can reduce the sampling rate by more than ten times.