Vertical Hybrid Integration Devices Using Selectively Defining Underneath Si Waveguide

3D hybrid integration based on III-V/Si waveguides by selective undercut wet etching (SUWE) of the lower Si layer has been demonstrated on a silicon-on-insulator (SOI) template. The process was performed on an adhesive-bonding material structure, defined by the upper InP/InAlGaAs (InAlGaAs quantum well) p-i-n heterostructure and the lower 220 nm SOI. After the top p-i-n III-V tapered waveguide was first fabricated and covered by Si ₃ N ₄ , KOH was then used for SUWE of Si layer from SiO ₂ and Si ₃ N ₄ , forming the bottom SOI single-mode waveguide. In comparison to monolithic III-V waveguide structure (InP based material), the simulated confinement factor of active region shows an enhancement from 10.3% to 16.7%. SOA/EAM devices were also processed and integrated in III-V layer, showing 7.2 dB optical gain at 70 mA injection current in SOA and 21.7 dB extinction ratio within 0~−2 V swing voltage in EAM. The strong quantum confined Stark effect (QCSE) in MQW confirms the improved confinement factor. It suggests a vertical self-alignment scheme could be used for realizing compact and submicron scale heterogeneous integration in a Si photonics template.