Miss Rate Estimation (MRE) an Novel Approach Toward L2 Cache Partitioning Algorithm’s for Multicore System

The concept of cache memory partitioning is handled and implemented few times earlier. Partitioning is essential in cache memory to attain still higher speed while searching and transaction of data, as L1 cache is comparatively small in size, memory interference in L1 cache is very low data, and instruction were partitioned easily. For effective use of multicore processor, cache partitioning or cache sharing is important. However, there are some limitations identified from many studies, like increase in simulation time, because of inter thread memory interfering, and inaccuracies in simulation. This paper explains a cache partitioning method for multicore systems using miss rate estimation. It reduces the interference of cache among concurrently executing process threads. The cache partitioning algorithm, using our novel approach, calculates the miss rate characteristics of individual threads at the run time, then dynamically partitions and distributes the cache memory among the threads, which are running concurrently, and thus improves the performance of multicore systems. The paper is divided into several sections; first, it explains all the basics related to the domain; secondly, it gives the details about all the papers which have been referred with a comparison. Finally, it focuses on future scope.