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A New Approach for Screening Retention Time Failure Bits in DRAM Device

Bonggu Sung,Daejung Kim,Yongjik Park,Joo-Sun Choi

International Symposium for Testing and Failure AnalysisISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis（2013）

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Abstract
Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.
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Key words
Non-Volatile Memory,Resistive Switching
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