A SiPM Readout Front-end with Fast Pulse Generation and Successive-Approximation Register ADC

A low-power front-end with on-chip fast pulse generation and customized 10-bit single-ended SAR ADC is developed for SiPM readout design. The on-chip fast pulse generation improves the timing resolution without the need of extra I/O pins. The proposed SAR ADC, reusing the SiPM charge integrator and eliminating the power-hungry charging sensitive amplifier, consumes significantly less power compared with conventional solutions. Designed in a 0.18 μm 1P6M bulk CMOS technology, the front-end contains 16 channels of SiPM readouts, and each channel consumes a power of 3.8 mW. With on-chip HPF to shape input signals, the fast pulse generation approach reduces the long-tailed SPE pulses width from 50 ns to 3 ns. At 16 MS/s, the SAR ADC consumes 743 μW from a 1.8 V supply and achieves a SNDR of 57.53 dB and a SFDR of 66.31 dB, respectively.