Minority Carrier Lifetime Extraction Methodology of SiC Epitaxial Layer

SiC has been focused as a strong candidate for high efficient power device semiconductors at high voltage regions1. Recent demonstrations of insulated gate bipolar transistors (IGBT) at a voltage over 15kV have proven the advantage of the use of SiC2. As the output characteristics are determined by the minority (hole) carrier lifetime (τp), measurement and control of the τp is utmost important. Optical methods are limited to measurements on separate wafers3, leading to differ from the real devices. In this presentation, we will propose an extraction methodology of minority carrier lifetime of an SiC epitaxial layer based on electrical measurement of pn diodes. The methodology is based on current measurements on parallel pn diodes with a spacing of W p under two different setups, shown in figure 1. The first one, named “single-setup”, is a setup measuring the center anode current while other anodes are kept open. The another one, named “multi-setup”, is a setup where all the anodes are grounded. The difference between the cathode voltage (V C) under same current, defined as ΔV, reflects the difference in the resistance of the n-base region. Based on device simulations with a 20μm-thick SiC epitaxial layer (N d=4.9×1015 /cm3) as an n-base region, one can find that ΔV is strongly dependent on the τp of the region (fig. 2(a) and (b)). Figure 3 shows the relationship between τp and ΔV at different W p. With this relationship one can obtain a τp precisely once the ΔV is experimentally obtained. In conclusions, we have proposed a methodology to extract the τp of an SiC epitaxial layer based on pn diodes with different setups. The proposed method allows us to estimate the τp with high precision. [1] M. K. Das, Mat. Sci. Forum, 600-603, pp. 1183 (2009). [2] W. Sung, ISPSD, pp. 271 (2009). [3] P. B. Klien, J. Appl. Phys., 103, 033702 (2008). Figure 1