(Invited) Gate-All-Around Nanosheet Field-Effect Transistors for Advanced Logic and Memory Applications: Integration and Device Features

We report on gate-all-around (GAA) field-effect transistors (FET) consisting of either vertically stacked lateral nanowires (NW)/nanosheets (NS) or vertical NW/NS for ultra-scaled, high-density logic and memory applications, respectively. The first type of GAA NS FETs is widely considered to be the most promising and mature candidate to replace finFETs for sub-5nm technology nodes in the logic roadmap. However, though sharing many fabrication elements, these devices face several specific technological challenges to enable their implementation into manufacturing, some of which will be addressed and evaluated in this paper. Furthermore, we will also present and discuss various critical integration features required to build vertical FETs, highlighting some of the key advantages feasible with the use of a replacement metal gate scheme in their fabrication flow, e.g.: shrinkage of the channel’s cross-sectional area for improved electrostatics, without impacting the source/drain (S/D) series resistances (RS/D); ION improvement thanks to stress-induced enhanced mobility values.