A 0.016 mm2 0.26-$\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOSJunheng Zhu,Woo-Seok Choi,Pavan Kumar HanumoluIEEE Journal of Solid-State Circuits（2019）引用 0|浏览5暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
