Leakage Engineering Enabling PDSOI Ring Oscillators Operating in Sub-100pA/µm I_off Regime

This work presents hardware demonstration of low power operation of PDSOI CMOS (Ioff down to ~10pA/µm at Vdd=0.9V, 45nm node) transistors, exhibiting successful operation of low leakage ring oscillators (channel and junction leakage ~30pA/invertor stage at Vdd=0.9V, 25C with 101 stages, pFET width=1.2µm, nFET width=0.8µm in each stage). The work highlights device and process feasibility study (through an asymmetric source/drain design) of enabling a PDSOI CMOS based low power application platform.