A 3.2-GHz 405 fs rms Jitter –237.2 dB FoM JIT Ring-Based Fractional-N Synthesizer

IEEE Journal of Solid-State Circuits(2022)

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摘要
A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divi...
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关键词
Synthesizers,Jitter,Quantization (signal),Phase locked loops,Clocks,Frequency synthesizers,Bandwidth
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