A low-power 6-bit successive approximation register ADC using a new split capacitor array method

In this paper, the design of a 6-bits successive approximation register (SAR) analog to digital convertor (ADC) in $0.18\ \mu \mathrm{m}$ technology is presented. This paper proposes the new SAR based on the monotonic switching structure for single-ended input signal. By using this method, the total number of capacitors, in the capacitor array is decreased. In addition, the special split capacitor structure is merged with the monotonic switching to considerably reduce the capacitor size. Using the split capacitor method, the switching energy can be reduced by 37%, while by adding the proposed method to the split capacitor method, it will be reduced to the half value of the split capacitor method. In addition, due to the existence of smaller capacitances than the conventional split capacitor method, the settling speed and input bandwidth increase. A dynamic comparator is used to decrease the static power consumption of ADC. In addition, very low power D-FFs based on transmission logic are used in the SAR control logic part to further reduce the power consumption.