HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers

ABSTRACTHigh-Level Synthesis can abstract away low-level circuits design and improve the coding productivity. However, it also lengthens the compilation time, exacerbating an already slow edit-compile-debug loop that discourages the development and refinement of FPGA accelerators. Partial Reconfiguration techniques can decrease the compilation time by reducing and parallelizing the size of the compilation task. But defining partial reconfigurable regions also needs expert layout-level knowledge, making this approach inaccessible to the high-level developers that HLS is intended to attract. To address the problems above, we propose HiPR, a framework that bridges the gap between HLS and PR. With HiPR, users can define a C/C++ function (rather than a Verilog module) as partially reconfigurable without considering detailed low-level constraints. HiPR automates the PR floorplan and allows the users to define elastic resource requirements for the C-level PR function for quick further tuning later. By mapping the full set of Rosetta Benchmarks, we show HiPR can find the proper floorplan solution within seconds and generate the overlay for later tuning. Significantly, the incremental compilation time can be accelerated by 3-10X with no performance loss.