A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units

Floating point operations are widely used in the fields of communication algorithm, digital signal processing, artificial intelligence and so on. However, the low computation speed and excessive resource consumption have become key limitations on system performance and hardware overhead. Thus, the area efficiency of floating point arithmetic units is important to accelerate computation and reduce resources. This paper presents high performance and area efficient floating point arithmetic units, including adder, multiplier and reciprocal operator. The proposed floating point arithmetic units are evaluated based on a typical scenario of $4\times 4$ matrix inversion in communication. Experimental results show that our designs achieved improvements on both performance and resource overhead. Compared with Xilinx Vivado IP, our designs save 20%-45% resources and only consumes 1/4 computing latency. Compared to DesignWare IP, our designs need only 1/4 computing latency, as well as improving area efficiency by 3.65 times.