Circuit Symmetry Verification Mitigates Quantum-Domain Impairments

IEEE Trans Signal Process(2023)

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Abstract
State-of-the-art noisy intermediate-scale quantum computers require low-complexity techniques for the mitigation of computational errors inflicted by quantum decoherence. Symmetry verification constitutes a class of quantum error mitigation (QEM) techniques, which distinguishes erroneous computational results from the correct ones by exploiting the intrinsic symmetry of the computational tasks themselves. Inspired by the benefits of quantum switch in the quantum communication theory, we propose beneficial techniques for circuit-oriented symmetry verification that are capable of verifying the commutativity of quantum circuits without the knowledge of the quantum state. In particular, we propose the spatio-temporal stabilizer (STS) technique, which generalizes the conventional quantum-domain stabilizer formalism to circuit-oriented stabilizers. The applicability and implementational strategies of the proposed techniques are demonstrated by using practical quantum algorithms, including the quantum Fourier transform (QFT) and the quantum approximate optimization algorithm (QAOA).
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Key words
Logic gates,Quantum circuit,Quantum state,Task analysis,Integrated circuit modeling,Switches,Qubit,Circuit-oriented symmetry verification,quantum error mitigation,quantum switch,spatio-temporal stabilizer,symmetry verification,variational quantum algorithms
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