15 kV/10 A SiC功率MOSFET器件设计及制备
Research & Progress of Solid State Electronics（2021）
Abstract
报道了在150μm厚、掺杂浓度5.0×1014 cm-3的外延层上制备15 kV/10A超高压SiC功率MOSFET器件的研究结果.对器件原胞结构开展了仿真优化,基于材料结构、JFET区宽度和JFET区注入掺杂等条件优化,有效地提升了器件的导通能力,器件比导通电阻为204 mΩ· cm2,击穿电压大于15.7 kV,在漏极电压15 kV时,器件漏电流为10μA,漏电流密度为12μA·cmz.在工作电压1.7 kV、导通电流10 A条件下,开通时间和关断时间分别为140 ns和84 ns.
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