Study on Digital Multiplier Architecture Using Square Law and Divide-Conquer Method

In this paper, we study digital multiplier architecture using a square law for obtaining the product AB from the sum and square of the inputs A and B and a Divide & Conquer method for small circuit implementation. We have designed them at the register transfer level (RTL) to confirm its operation. We have investigated the squaring calculation circuit with look-up table (LUT) and also direct squaring calculation logic. We show that in case of the squaring law usage, the Divide & Conquer method can be utilized in both cases of squaring calculation circuits with LUT and direct logic, and it can reduce the circuit. The digital multiplier is widely used for digital computers and DSP chips. When it is realized directly, a two-dimensional array of full adders is required; as the number of bit increases, its circuit size and power become large and its computation time is also increased. The investigated architecture is expected to solve these problems.