Design and Implementation of 15-Level Asymmetric Ca scaded H Bridge Multilevel Inverter

This paper presents a Design and Implementation of 15-Level Asymmetrical Cascaded H Bridge Multileve l Inverter. In this system Symmetrical and Asymmetrical Multilevel inverter (MLI) is utilized. In Symmetrica l MLI, the DC source magnitude’s are equal ie., 60V dc, 60Vdc ,60Vdc &60Vdc.,where as in Asymmetrical MLI the DC source Magnitude’s are unequal and it is designed with bin ary form of voltage such as 33V dc, 66Vdc & 132Vdc.Comparing both the MLI , Asymmetrical MLI generates a number of output voltage level with same number of Power semiconductor switches. Th e phase Disposition Pulse Width Modulation (PD-PWM) technique is used for controlling the Power semiconductor switch es in MLI. The results are verified in MATLAB, PROTEUS and real time system Keywords—Photo voltaic system(PV), Symmetrical MLI , Asymmetrical MLI, PD-PWM,PIC16F877A,IR112.