A Feasibility Study on Realizing General-purpose Technology Mapper for DSPs of FPGAs Using Exhaustive Search

This paper proposes a technology mapping algorithm applicable for arbitrary single-output tree-structure DSP block whose operation nodes have up to two fan-ins of FPGAs, based on an exhaustive search to find an optimal implementation of the given application circuit description. DSP blocks consisting of hard macro multipliers, etc. have become essential in FPGAs to achieve high performance and area efficiency. For the effective use of DSP blocks, a technology mapping algorithm is indispensable to find the optimal implementation of a given circuit using DSP blocks. Ronak et al. have proposed a greedy algorithm to search for a mapping that maximizes throughput, targeting the Xilinx DSP48E1. Our proposed algorithm applies to a broader range of DSP blocks since it automatically generates a database of valid configurations from a structural description of the target DSP block. Replication of the operators allows us to find solutions with a smaller number of DSP blocks than those by the conventional algorithm while reducing global nets. To reduce runtime, we also introduce pruning techniques and graph partitioning that do not affect the optimality. From experiments using DFGs with 33, 58, and 100 nodes, the proposed method reduces the number of DSP blocks by 7.94–10.81% compared with the conventional algorithms.