Session 6 Overview: Ultra-High-Speed Wireline

2:00 PM 6.2 A 60Gb/s 288mW NRZ Transceiver with Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65nm CMOS Technology J. Han, University of California, Berkeley, CA In Paper 6.2, the University of California at Berkeley presents a 60Gb/s NRZ transceiver. A new baud-rate CDR is proposed to enable energy efficient CDR operation. Implemented in a 65nm CMOS technology, the design achieves a 60Gb/s data-rate with 30% eye opening at BER < 10 while consuming only 288mW. Subcommittee Chair: Frank O’Mahony, Intel, Hillsboro OR