A 4-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC

Ian Assom,Gerardo Salgado,Daniel O’Hare, Keith A. O’Donoghue

semanticscholar(2021)

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摘要
This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and FiniteImpulse-Response (FIR) DAC to have inherent Inter-SymbolInterference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-NoiseDistortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4 order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4. 2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal
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