Optimization of Speed and Power by using 14T SRAM Single and 8 Bitcell

1PG Student, Dept. of ECE, PGP college of Engineering and Technology, Tamilnadu, India 2Assistant professor, Dept. of ECE, PGP college of Engineering and Technology, Tamilnadu, India 3Assistant professor, Dept. of ECE, PGP college of Engineering and Technology, Tamilnadu, India 4Assistant professor, Dept. of ECE, PGP college of Engineering and Technology, Tamilnadu, India ---------------------------------------------------------------------***----------------------------------------------------------------------ABSTRACTFor radiation hardening, using 14T SRAM bit cell, which circuit and layout level optimization design in a in a 65-nm CMOS technology increased pliability to single-event upset (SEU) as well as single-event–multiple-node upsets (SEMNUs) due to the charge sharing among OFF-transistors. In this proposed design of RSP-14T by 8-bit SRAM cell, which performance better than existing design of RSP-14T per bit. In this design CMOS transistors which is used to store the data. In the radiation environment, when the heavy ion incident occurs on the semiconductor material, the particles will be ionized. These excess charges will be collected by the sensitive nodes of the device. As a result, a voltage perturbation will appear at those nodes. For SRAM bit cell, when the amplitude of the voltage perturbation is strong enough and exceeds the logic threshold level of the inverter, the data stored might be turned over. By using this concept of 14T SRAM design will give the better result of power, area and delay than the existing system. Finally, the proposed design is implemented in the TANNER EDA at 45nm CMOS Technology with 0.9V input voltage and proved the comparison in terms of area power and delay.