A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS.

We present a wireline transmitter (TX) for reconfigurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer ((CMOS)-M-2 MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (f(max)/f(min) = 110x). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10(-12) with a 60.9-ps eye width.