Enabling Monolithic Heterogeneously Integrated Si/III-V Technology Platform.

This paper presents an overview of the SMART-LEES (Singapore MIT Alliance for Research and Technology – Low Energy Electronic Systems) research program that integrates Si and III-V devices for heterogeneously integrated Si/III-V technology platforms in a single chip. It shows a novel approach to the Si/III-V front-end-of-line (FEOL) integration process with a unique way for forming electrodes on device terminals to multilevel metal wires in the back-end Si/III-V process.