A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

Hyungmin Jin,Jindo Byun,Hyunyoon Cho,Hojun Yoon,Jin-Hee Park, Kyoungsoo Kim,Youngdon Choi,Jung-Hwan Choi,Hyungjong Ko,Sang-Hyun Lee

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)（2021）

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摘要

The memory I/O interface needs to achieve two conflicting requirements: increasing I/O bandwidth and reducing energy consumption at the same time. To achieve these goals, memory interface is now rapidly moving from Non-Return-to-Zero (NRZ) to Pulse Amplitude Modulation-4 (PAM-4) [2]. However, the test infrastructure for PAM-4, such as ATE, which is the most important factor in memory mass producti...

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关键词

Performance evaluation,Mass production,Power supplies,Memory management,Jitter,Hybrid power systems,Solid state circuits

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