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A 1596gb/s 48gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration.

IEEE solid-state circuits letters(2022)

Cited 4|Views25
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Abstract
A 384-Keccak cryptographic cores system on chip (SoC) (die size > 800 mm 2 and reticle size > 25.5 mm $\times $ 32.0 mm) with 48-Gb stacked embedded DRAM (SeDRAM) is presented using 110-K/mm 2 integration density and 0.1-fF capacitive load hybrid bonding integration. The SeDRAM’s advantages of low power and low latency are fully utilized by 49152 wide-IO and network-on-chip design in logic. Thermal stress and reliability are resolved to get a high package yield. The proposed SoC consumes 1596-GB/s bandwidth with 55-W power consumption only and achieves a great system performance improvement.
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Key words
Bandwidth,hybrid bonding (HB),performance,stacked embedded DRAM (SeDRAM),system on chip (SoC)
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