An Improved Multicarrier PWM (MCPWM) Technique With a New Harmonic Mitigation Strategy for Cascaded H-Bridge Multilevel Inverter Applications

The conventional modulation schemes of the cascaded H-bridge dc/ac converter generate a higher percentage of low-frequency harmonics at the output voltage and lead to discontinuous high-peak output current that causes a detrimental effect on the industrial motor drive systems. Addressing this concern, this article proposes an improved multicarrier pulsewidth modulation (MCPWM) technique that reduces harmonic content from the ac output voltage while achieving continuous output current with reduced peak magnitude. The proposed technique introduces a harmonic mitigation algorithm that adopts the switching angles of the MCPWM pulse to support the online adjustment of the modulation index and the switching frequency of the semiconductor switches. The main emphasis of this research is to mitigate the fifth, seventh, and eleventh order harmonics from the inverter output voltage and to define a new range of switching angles where the respective harmonics exhibit the lowest amplitude. Moreover, the work offers a novel approach to estimate the switching angles of the MCPWM pulse-train in real-time operation without solving the complex nonlinear equations. The proposed modulation technique has the benefits of low-frequency harmonic mitigation, low-processing time, and requirement of a minor segment of medium-sized FPGA, thereby it provides a good tradeoff between complex design and better performance. The feasibility and effectiveness of the proposed technique have been identified by a comprehensive comparison with the recently-reported schemes. Furthermore, theoretical, simulation, and experimental results using an FPGA-based three-phase cascaded H-bridge multilevel inverter prototype are included to justify the suitability of the proposed technique.