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An Analytical Model of Read-Disturb Failure Time in a Post-Cycling Resistive Switching Memory

Cheng-Min Jiang,Chih-Chieh Wang,Kai-Shin Li,Chao-Cheng Lin,Tahui Wang

IEEE Transactions on Device and Materials Reliability（2021）

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Abstract
We characterize SET/RESET cycling effects on read-disturb failure time in the low resistance state (LRS) of a hafnium-oxide resistive memory cell. We find that the read-disturb failure time degrades by orders of magnitude after SET/RESET cycling. An analytical LRS read-disturb failure time model including cycling induced trap generation rate and its influence on read-disturb characteristics is dev...
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Key words
Degradation,Voltage measurement,Stress,Switches,Analytical models,Time measurement,Reactive power
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