A 0.1–9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2021)

引用 4|浏览8
暂无评分
摘要
This article describes a design for a frequency synthesizer architecture based on a phase-locked loop (PLL) for avionic software-defined radio (SDR) applications at up to 9 GHz. Three basic architectural schemes: wide range voltage-controlled oscillator (VCO), single sideband (SSB) mixing, and multiple VCOs can be used to extend the frequency ranges. This article compares these schemes through qua...
更多
查看译文
关键词
Frequency synthesizers,Voltage-controlled oscillators,Synthesizers,Phase noise,Phase locked loops,Aerospace electronics,Amplitude modulation
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要