Interface Admittance Measurement And Simulation Of Dual Gated Cvd Ws2 Moscaps: Mapping The D-It(E) Profile

Dual gated 2ML WS2 MOS Capacitors have been fabricated with capacitance values as high as 2.7uF/cm(2) (with single sheet charge centroid assumption for the WS2 channel). Frequency and temperature dependent C-V measurements were correlated with simulations to extract the interface trap density-energy (D-IT(E)) profile. We observe an exponentially decaying defect distribution from the conduction band (E-C) edge with a magnitude of 8 x 10(13) cm(-2) eV(-1) and an inverse slope of 0.12 eV and a similar distribution with a peak magnitude of 1.2 x 10(14) cm(-2) eV(-1) from the valence band (EV) edge with an inverse slope of 0.12 eV.