Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

This paper characterizes the Single Event Effect (SEE) sensitivities of the Serializer/Deserializer (SerDes) module on the advanced 28 nm Xilinx Kintex-7 Field Programmable Gate Array (FPGA). A systematical SEE measurement method is proposed and implemented to evaluate the SEE sensitivity of the SerDes circuits. In our experiments, an extremely low Single Event Upset (SEU) Linear Energy Transfer (LET) threshold of the SerDes circuits was investigated, and both the recoverable and unrecoverable Single Event Functional Interrupts (SEFIs) were clearly distinguished and classified. In the experiments, it was found that the SEUs and recoverable SEFIs of the TX and RX in the same channel were closely related due to their shared clock and control circuits. Based on this detailed survey, a further discussion of the mechanisms of the SEU, recoverable SEFI, and unrecoverable SEFI is also provided. The SEE sensitivity of the high-speed SerDes circuits presented in this paper will promote the effective utilization of error mitigation strategies in order to control the risks of applications in radiation environments.