A method to prevent hardware Trojans limiting access to layout resources

The advancement of Integrated Circuit (IC) technology has encouraged the IC industries to go fabless and outsource the fabrication to other companies, due to the cost associated with installing a new facility and design to production time limitations. It has also introduced an adverse effect on hardware security, known as Hardware Trojan (HT), which is very difficult to detect due to low signal-to-noise (SNR) ratio. As a result, Hardware Trojan has become a serious concern for the semiconductor industry. Even though researchers have proposed various solutions and design methods to address these security concerns, due to the wide range of Trojans, a comprehensive solution to counteract these security threats is yet far from reach. For now, only specific solutions for certain Trojan detection have been presented. Different Trojan prevention methods have also been explored with optimal hardware security in mind. In this article, a novel Design-For-Security (DFS) idea for HT prevention has been presented where the unused polysilicon layer is occupied using minimum feature wires and thus deprive the attackers of the resources needed for Trojan routing. The main advantage of this technique is that it prevents an attacker from inserting any active layer in the silicon substrate, which is a fundamental component of any CMOS device. Since the active layer connects directly to any polysilicon layer, if the unused polysilicon layer is covered with minimum feature wire, it is impossible for attackers to rout any extra circuitry without removing a portion of the polysilicon wire. A readout circuit is used to determine the delay produced by the added polysilicon wires, which in turn makes sure that the polysilicon layer is intact, and it has not been tampered with. A unique signature is also obtained using those polysilicon wires as probes to induce signal from the main circuit. Any modification to either the circuit or the polysilicon probe will reflect a change in the signature. Simulation results indicate that with a proper design, even the insertion of a single inverter can be detected. This technique can ensure 100% utilization of the empty spaces in the polysilicon layer.