Investigation of BiFeO 3 /HfO 2 gate stack for ferroelectric field effect transistors in IOT applications

We present the fabrication and characterization of a metal-ferroelectric-insulator-silicon field effect transistor (MFIS-FET) for high-speed and non-volatile memory applications. Ferroelectric BiFeO 3 and high-k dielectric HfO 2 films were deposited by the radio frequency sputtering and integrated on the silicon substrate to realize the FET structure. BiFeO 3 film of a constant thickness (200 nm) and HfO 2 film of varying thickness from 5 to 20 nm was selected for the different capacitor structure fabrication and parameter optimization. Structural characteristics of the BiFeO 3 film were obtained using x-ray diffraction (XRD) and scanning electron microscopy. Structural characteristics show the ferroelectric film of polycrystalline structure with the grain size of ≈ 26 nm at the annealing temperature of 500 °C. The ferroelectric film optimization was carried out at different annealing temperatures to obtain the crystalline structure. Effect of insulator layer thickness on the MFIS structure memory window (MW) and leakage current density was investigated to select an optimized buffer layer thickness for the FET fabrication. MFIS-FET with 10 nm buffer layer was fabricated from the optimized parameters that show a MW of 26.7 V and the drain current ON–OFF ratio higher than 10 6 for the voltage sweep of ± 30 V.