Fan-Out Wafer Processing In The High Density Packaging Era

In an age where we are witnessing the emergence of high power computing requirements for a variety of applications, Fan-Out Wafer Level Packaging (FO-WLP) technology is an increasingly popular solution for obtaining a high level of device integration with a greater number of I/O contacts, in a small package. First introduced for small die applications such as power management and RF transceivers, it now serves as a platform for mobile application processors. There are many different FO-WLP schemes in use, all aimed at achieving better device performance in a smaller/thinner/cheaper package. While the different schemes vary in their detail, in simple terms, they all involve embedding die in a cost-effective epoxy mold substrate with metal redistribution layers (RDL) forming the interconnects between die and bump connections.Prior to UBM/RDL metallization by physical vapor deposition (PVD), the mold substrate needs to be degassed and native oxide needs to be removed from the metal contacts, within the relatively low thermal budget imposed by the epoxy mold. Due to a lower ion energy, Inductively Couple Plasma (ICP) etch processing induces less heating and lower levels of contamination from any organics on the substrate during the removal of the oxide, than alternative “diode” plasma etching solutions. Data will be presented showing long time between chamber cleans, and how a novel in-situ pasting technique gives low & stable contact resistance.