Challenges of TSV backside process integration

Catharina Rudolph,Holger Wachsmuth,Mathias Boettcher,Wolfram Steller,M. Juergen Wolf

2015 International Conference on Planarization/CMP Technology (ICPT)（2015）

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摘要

New challenges have to be mastered with the introduction of Through Silicon Vias (TSVs) as a key element in 3D integration. This includes also the development and validation of various types of assembly and packaging concepts and methods. The investigations discussed here have been conducted on an interposer for sensor and CMOS devices.

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关键词

TSV backside process integration,through silicon via,3D integration,CMOS device,silicon interposer,RDL layer,test pad,polyimide isolation,copper landing pad,silicon carrier wafer,bond adhesive,oxide coating,polyimide material,slurry,self-adjusting integration scheme,temporary bonded wafer,polymer CMP,chemical mechanical polishing,complementary metal oxide semiconductor,size 300 mm,Ni-Au,Cu-SnAg

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