A Novel Design To Reduce Reflection For Bi-Directional Multi-Dimm Memory Channels
2018 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL INTEGRITY AND POWER INTEGRITY (EMC, SI & PI)（2018）
Abstract
This paper proposes a method to reduce the stub reflection effects on a memory channel of a server platform. The memory channel eye height and eye width margin improved by 3 times when isolation between multiple dimms were achieved. Balanced margin distribution between dimms were also accomplished. Process, voltage and temperature (PVT) variations were improved as well.
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Key words
memory channel, DDR4, DDR5, server, signal integrity, simulation, reflection
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