A Novel Low-Voltage Biasing Scheme For Double Gate Fbc Achieving 5s Retention And 10(16) Endurance At 85 Degrees C

We demonstrate a novel low-voltage biasing scheme on ultrathin BOX (UTBOX) FDSOI floating body cells with L-g=55nm and t(Si)=20nm. By optimizing the front and back gate biasing to enhance the positive feedback loop, the required V-DS can be reduced to 1.5V while retention times as high as 5s can still be achieved at 85 degrees C. For the first time, we also show that the stringent endurance spec of 10(16) cycles can be met as a result of the V-DS reduction.