A 103fs(Rms) 1.32mw 50ms/S 1.25mhz Bandwidth Two-Step Flash-Delta Sigma Time-To-Digital Converter For Adpll

Ying Wu, Ping Lu,Robert Bogdan Staszewski

PROCEEDINGS OF THE 2015 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC 2015)（2015）

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摘要

A 50-MS/s two-step flash-Delta Sigma time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fs(rms), which is equal to an equivalent resolution of 1.6 ps.

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关键词

Noise shaping, time domain register, error feedback, time-interleaved, time-to-digital converter, MASH

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