A Study On Error Corrected Code (Ecc) Failure Induced Latent Defect In Between High-K Mim Capacitors

For fault management, various types of error-correcting codes (ECC) have been widely used for most computers and memory. From a memory perspective, the ECC technique is generally adopted for DRAM modules to correct data corruption among multiple chips, not in-chip level. Recently, increased soft single-bit failures have accelerated introduction of the ECC technique into DRAM components. For reliability, fault generation technique by high voltage at high temperature, also known as burn-in stress, has been widely used in the IC manufacturing process. In DRAM, burn-in stress is also useful to screen latent defects or to predict device lifetime. In this paper, we studied un-correctable errors which occurred due to various types of storage node bridge defects in ECC DRAM. 12 faulty cells among 1,000 cells are observed after burn-in stress. Retention time of each cell is measured with automatic test equipment under the various temperature conditions, and activation energy were extracted from measurement results. Results of activation energy show that there were two types of faults, one was metal-metal hard bridge (0.14eV) and the other was dielectric-dielectric soft bridge (0.35eV), in comparison with normal cells (0.53eV). Moreover, soft bridge was carefully analyzed with TEM and nanoprobing showing that activation energy analysis was well-matched.