A Fully Differential 11mw 10-Bit 200ms/S Sample And Hold In 0.25 Mu Bicmos Technology

A fully differential low power 10-bit 200MSPS Sample and Hold has been designed for the front-end of a pipetined analog-to-digital converter using 0.25 mu m BiCMOS technology. Switched capacitor differential topology has been used with special care taken in linearization of switches. The key issues of the design are optimization of speed, accuracy and power minimization. An op-amp (OTA) having very fast settling time of 1.67ns is designed to meet the speed requirement of the Sample and Hold. The sample and hold consumes 11mW power while occupying an area of 0.07 mm(2) including clock driver circuitry. Analog and digital powersupplies used are 3V and 2.5V respectively.