Novel architecture for area and delay efficient vedic multiplier

Multipliers are a crucial components in various computations involved in Digital Signal Processing (DSP). Various multiplication schemes have been proposed in the past like Array, Booth and Wallace Tree. However at present multipliers based on Vedic mathematics are under research because of their high performance in terms of area and delay. The use of fast adders enhances the speed of Vedic Multipliers at the cost of increased area as proposed in various literatures. This paper however explores an architecture which gives lesser delay and lesser increase in area on use of such fast adders.