A Low Power 25ms/S 12-Bit Pipelined Analog To Digital Converter Foil Wireless Applications

A 12-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 um CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12-bit resolution and settling in 20ns within 0.05% accuracy. However Pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total Power dissipation is about 76mw from a single 3v supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. SNDR of 70.1 dB is achieved.