A 10ghz Tcp Offload Accelerator For 10gb/S Ethernet In 90nm Dual-V-T Cmos

Y Hoskote,V Erraguntla,D Finan,J Howard,D Klowden,S Narendra,G Ruhl,J Tschanz,S Vangal,V Veeramachaneni,H Wilson,Jp Xu,N Borkar

2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS（2003）

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摘要

This prototype offloads TCP input processing on minimum packet sizes at wire speed for 10Gb/s Ethernet. The design employs a 10GHz core with a specialized instruction set and includes hardware support for dynamically reordering packets. In a 90nm dual-V/sub T/ CMOS process, the 8mm/sup 2/ chip has 260K transistors. Simulation predicts a power dissipation of 1.9W at 1.2V and 10GHz.

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关键词

CMOS digital integrated circuits,local area networks,microprocessor chips,transport protocols,1.2 V,1.9 W,10 GHz,10 Gbit/s,90 nm,Ethernet,TCP offload accelerator,dual-V/sub T/ CMOS process,dynamic packet reordering,instruction set,microprocessor chip,

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