A 0.003-Mm(2) 50-Mw Three-Stage Amplifier Driving 10-Nf With 2.7-Mhz Gbw

D. Marano, A. D. Grasso,G. Palumbo, S. Pennisi

23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016)(2016)

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摘要
This paper presents a power- and area-efficient three-stage amplifier suitable to drive high capacitive loads. The amplifier is compensated by a single Miller Capacitor and an additional feedforward stage. To improve the amplifier large signal transient response, the topology also includes an external feed-forward path and a novel slew-rate enhancer section. Implemented in a 0.35-mu m CMOS process, the amplifier occupies less than 0.003-mm(2) of die area. When driving a 10-nF load, it provides 2.7-MHz gain-bandwidth product and 0.55-V/mu s average slew-rate, while consuming only 25-mu A quiescent current from 2-V supply.
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关键词
CMOS analog integrated circuits,operational transconductance amplifiers,multistage amplifiers,frequency compensation
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