High Performance Cmosfet Technology For 45mn Generation
2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS(2004)
Abstract
High performance CMOSFET process design for 45nm generation is demonstrated. Activation process policy is shown for the first time to achieve high performance source and drain extension (SDE) junction, high gate activation and defect-less source and drain (SD) junction simultaneously for 45nm generation technology. Most serious problem of phosphorus TED is investigated in detail and suppressed by appropriate designing of activation process. Good Vth roll-off and Ion-Ioff characteristics are achieved for 20nm gate MOSFET by utilizing ultra high speed annealing technique, disposable sidewall spacer, phosphorus n+ SD and appropriate designing of activation process.
MoreTranslated text
Key words
high performance cmosfet technology
AI Read Science
Must-Reading Tree
Example
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined